1. Field of the Invention
The invention relates to integrated circuit devices and more particularly to voltage regulation on such devices.
2. Description of Related Art
Modern integrated circuits are designed for very low power operation. The use of complementary metal oxide semiconductor (CMOS) devices, which have low static power consumption, has allowed this low power operation. The use of CMOS structures facilitates further reduction in power as integrated circuits move from an operational standard of 5 volts to operate at 3.3 volts.
As a consequence of designing circuit chips to operate at a lower supply voltage (e.g., 3.3 volts), chip manufacturers have had to accommodate the requirements of, for example, chip users, such as computer manufacturers and others, that have designed their devices to operate at a higher supply voltage (e.g., 5 volts). Thus, in lower voltage chips, the supply voltage must be regulated.
In the past, regulation has been achieved by external regulators added to systems, such as computers or other equipment, that regulate the voltage down to the required supply voltage for the chip for an active or operational mode.
In addition to the active or operational mode, most CMOS chips are expected to be able to go into a passive or power-down mode of operation. The power-down mode conserves power and is very useful in portable systems. In the power-down mode, the integrated circuits of a chip are expected to retain some information, for example, a memory of the status of particular circuits.
In the power-down mode, there is generally minimal or no current flow. Nevertheless, the power-down mode requires that the supply voltage in which the chip is operating must stay at the required supply voltage, e.g., 5 volts or 3.3 volts, to retain information. The power-down mode is a static mode of operation as explained herein using a CMOS structure, an inverter, as an example. An inverter consumes power when switching states. Thus, a low to high signal to an inverter, for example, 0 volts to 3.3 volts, causes the inverter to generate an opposite output, i.e., high to low, e.g., 3.3 volts to 0 volts. This is called inverter switching; the inverter switches from one state to another state. Inverter switching consumes power, i.e., to switch states consumes power. When an inverter is maintained at a steady state, i.e., a non-switching state, for example, low, the inverter output maintains its state at high. In this scenario, the inverter does not consume any power whatsoever. The inverter still must have a supply voltage, e.g., 3.3 volts, to maintain the static state. Thus, in static states, CMOS circuits consume virtually no power. In a dynamic state, a circuit will consume power, for example, to change in mode from high to low. The static state is what is entered into in the passive or power-down mode.
Additionally, the flexibility of a "bypass" mode of operation is desirable in systems transitioning from one operating voltage to another. In this mode, the input power supply voltage is transmitted directly to the output of the regulator, effectively bypassing the regulator's functionality.
No implementation of CMOS on-chip regulators incorporating the above-mentioned modes of operation has been contemplated by prior art circuitry.